A delay-locked loop (DLL) is a digital circuit that can be used to change (e.g., modulate) a phase of a clock signal (e.g., a signal with a periodic waveform). A DLL is typically used to enhance a clock's timing of an integrated circuit (such as memory controller) to ensure that when a 1 is transmitted to a memory bank a 1 is received (e.g., latched) at the memory bank. If timing is off, a transmitted 1 could be received as a 0.
On a single or multi-load bus (e.g., a bus that serves multiple dynamic random access memory circuits), conventional systems seek to deploy a common DLL. In fly-by topology, a worst-case setup time on the load with the smallest electrical flight time from the memory controller and the worst-case hold time on the load with the largest electrical flight time from the memory controller may dictate significant DLL displacement if each pattern on each load is considered exclusively. As such, conventional methods place the common DLL midway between the low and high DLL limit for the load(s).
Current memory architecture, such as DDR3, may utilize training to determine a common DLL placement for a single or multi-load bus. However, the available timing margin for placing a common DLL diminishes when signaling at higher speeds.